Bhargav Shrivathsa

H.264 encoding on the IBM Cell/B.E. processor

Here, you'll find information regarding the H.264 video encoder project that Bhargav completed as part of a five-person team in the Fall of 2008 for his class on multicore processors.

Project Description

This project's goal was to port an existing implementation of the H.264 video encoding algorithm onto the IBM Cell processor and optimize the motion estimation kernel of the algorithm using the parallelism enabled by the eight SPEs, as well as exploiting other advantages offered by the Cell architecture.

Report and Source Code

The project report is available here (warning, 1.0 megabyte PDF). The source code is also available (warning, 6.0 megabyte zipfile).

Acknowledgment

Bhargav would like to thank adjunct faculty member Prof. Lurng-Kuo Liu for his suggestion of this topic, his support during the project, and for ingraining the idea of "calculated risk-taking" necessary while handling projects of this complexity.

Designing a clock and power distribution mechanism for a high-speed 16-core Network on Chip

Here, you'll find information regarding Bhargav's digital VLSI circuits project completed in Spring 2008. This team effort was led by Prof. Kenneth Shepard and Prof. Luca Carloni, focusing on designing a high-bandwidth communication system for a Network on Chip (NoC) architecture.

Project Description

The goal was to design a clock and power distribution mechanism for all the cores on the chip. An H-tree-driven grid was used for the clock distribution, shielded by the power grid. Both the tree and grid were generated using Cadence SKILL code in Cadence Virtuoso Layout, with manually designed buffers verified in Cadence Virtuoso Schematic. The project utilized 90nm IBM CMOS technology provided via a student NDA through MOSIS.

Report

The project specification contains unpublished proprietary information and is not available online.

Acknowledgment

Gratitude is extended to Prof. Shepard for his project-centric approach and professional technical design setting, as well as to course TA Omar Ahmad for his technical assistance.

Implementing high-speed 128-bit AES decryption on an FPGA

Here, you'll find information regarding Bhargav's embedded system design project completed in Spring 2008 as part of a four-man team.

Project Description

The team initially set out to decrypt a single image from an SD card but expanded the scope to decrypt a series of images at the suggestion of Prof. Stephen Edwards. Bhargav focused on pixel decoding, integrating the high-level processor, and managing the timing-critical SRAM-VGA interaction.

Report and Additional Resources

The project report is available here (warning, 1.0 megabyte PDF). Further documentation, a comprehensive report with code, the design proposal, and the final presentation are located on the course webpage.

Acknowledgment

Special thanks are extended to Prof. Edwards for advocating a milestone-driven timeline and encouraging the team to surpass their initial goals, as well as to David Lariviere, the course TA, for his technical support.

Building a Wireless Time Sync Simulator

Here, you'll find information regarding Bhargav's wireless networking project that he coded in the Spring of 2008.

Project Description

Exploring different time sync mechanisms in a wireless network, Bhargav developed an event-queue-driven, cycle-accurate simulator coded in C to simulate network nodes with randomized transmission ranges and positions, aiming for network time synchronization.

Report

The project report is available here (PDF). The source code is not available online.

Acknowledgment

Bhargav extends his gratitude to Prof. Gil Zussman for the encouragement to pursue a novel research topic—RBS in an MPR environment.

Hardware/software co-design of an FPGA-based MP3 decoder

Here, you'll find information regarding Bhargav's distributed embedded systems project completed as part of a two-man team in Spring 2008.

Project Description

This project involved implementing an open-source MP3 decoder on the Altera Cyclone II FPGA. The project aimed to integrate the longstanding MP3 format with the relatively new FPGA technology, focusing on understanding the intricacies of hardware/software co-design.

Report

The project report is available here (warning, 1.0 megabyte PDF).

Acknowledgment

Bhargav extends his gratitude to Prof. Carloni for suggesting the project and to David Lariviere for his technical assistance throughout the project.

Designing an SRAM array at the 90 nm tech node

Information about the VLSI project completed in the Fall of 2007 can be found here. The project aimed to create a 64x64 SRAM cell array using 90nm IBM CMOS technology.

Project Description

The project involved creating a 4 kilobyte array of 6-transistor SRAM cells, along with the necessary circuitry for reading, writing, and precharging. The work included making design choices between static and dynamic logic and considering speed and testability. The schematic was built in Cadence Virtuoso Schematic, tested using Cadence Analog Design with Spectre as the simulator, and laid out in Cadence Virtuoso Layout.

To maximize speed and minimize area, domino logic was used, achieving a maximum frequency of around 1.4 GHz for the dynamic address decoder. The design passed all necessary checks, including Design Rule Checking (DRC) and Layout Vs Schematic (LVS) in Cadence.

Report

The project report is available here (warning, 2.0 megabyte PDF).

Acknowledgment

Special thanks are extended to adjunct faculty Azeez Bhavnagarwala for proposing this project and to course TA Omar Ahmad for his technical support.

Removing vocals from commercial tracks

Here, you'll find information regarding Bhargav's DSP project completed in Fall 2007 with his partner Jaime Peretzman.

Project Description

The project aimed at removing vocals from commercially-mixed audio tracks, exploring three different methods:

• Bandpass filtering - Targeting the frequency range of the human voice.
• Stereo cancellation - Involves canceling common frequencies between stereo channels.
• STFT and Binary masking - Advanced research involving Blind Source Separation.

This project was designed and implemented in MATLAB.

Report and Resources

The project report is available here. All project assets, including MATLAB code and audio samples, are available as a .zip file. The MATLAB code can also be downloaded here.

Acknowledgment

Thanks are extended to Prof. Dan Ellis for his guidance and approval of this ambitious project.

Designing a low-power, high unity-gain-bandwidth op-amp

Here, you'll find information regarding Bhargav's analog circuits project that he completed in the Fall of 2007.

Project Description

The goal was to design an operational amplifier to be used in a low pass filter. The specifications were very clear-cut, with bonuses for hitting certain high specs. The schematic was built and tested using Cadence tools and 130nm IBM BiCMOS technology through MOSIS.

Report

The project report is available here (PDF). Supplemental material such as graphs are not part of the online report.

Acknowledgment

Bhargav would like to thank adjunct faculty Timothy Dickson for emulating a real-world scenario for the project, and course TA Colin Wu for his commitment to resolving student issues.